Photo-sensitive electronic components can be used to create electronic imaging systems, including systems for detecting and measuring motion. One application for motion detection is a computer pointing or input device, such as a computer mouse. Use of electronic imaging for such purposes is described in, e.g., U.S. Pat. Nos. 6,303,924 (titled “Image Sensing Operator Input Device”) and U.S. Pat. No. 6,172,354 (titled “Operator Input Device”). As described in those patents, an array of photo-sensitive elements generates an image of a desktop (or other surface) portion when light from an associated illumination source (such as a light emitting diode) reflects from the desktop or other surface. Subsequent images are compared, and based on the correlation between images, the magnitude and direction of mouse (or other device) motion may be determined.
FIG. 1 shows a pixel 1 within a photo-sensor array architecture used in existing computer input devices. Each pixel of the photo-sensor array includes a photo-sensor 2, which may be a photodiode or other photosensitive component. Prior to obtaining an image, assertion of a RESET signal on NMOS transistor 3 charges node INT to a reference voltage VREF. The RESET signal is then disengaged, and light reflected from a desktop or other surface illuminates photo-sensor 2. A reverse bias current flows to ground through photo-sensor 2, and node INT is then discharged as a result of the reverse bias current. Higher intensity (or brighter) light, which may correspond to a more reflective object or surface feature, allows a greater reverse bias current through photo-sensor 2, and thus a more rapid discharge of node INT. Conversely, lower intensity (or dimmer) light, which may correspond to reflection from a darker object or surface feature, allows a smaller reverse bias current through photo-sensor 2, and a less rapid discharge of node INT. The voltage on node INT controls the gate of NMOS transistor 4; as the charge on node INT is drained, the correspondingly decreasing bias on NMOS 4 causes a drop in the voltage at node 5. At a designated point in time, a SELECT signal is applied on the gate of NMOS 6, permitting a charge to accumulate on either of storage capacitors 7, depending on the state of selection NMOS devices 13 and 14. The voltage across NMOS 4 varies with the gate voltage on NMOS 4, which in turn varies with intensity of illumination upon photo-sensor 2. Thus, the magnitude of the accumulated voltage on storage capacitor 7 relates to the magnitude of the illumination upon photo-sensor 2. Because the intensity of the reflected illumination will vary based upon surface features of a desk or other surface, this charge on storage capacitor 7 can be used (as part of an array of similar photo-sensor pixels and storage elements) to detect and measure changes of position with regard to that desk or other surface.
The two NMOS selection switches 13 and 14 allow the above cycle to be performed twice. The first time the sequence is performed, NMOS switch 13 is enabled and (preferably) a known amount of light is used to illuminate the complete array. This known amount of light is typically chosen to be a dark image, i.e. no light. The second time the sequence is performed, NMOS switch 14 is enabled and NMOS switch 13 is disabled. In the second sequence, a normal light exposure is used to illuminate the photo cell. The subsequent processing of the image is performed by comparing the information stored on the capacitor connected to NMOS switch 13 to the information stored on the capacitor connected to NMOS switch 14. The process of comparing the difference of these two capacitor values is called Correlated Double Sampling (CDS), and permits cancellation of errors associated in the storing of the charge on the capacitors. Because the error was the same during both sequences, the error terms cancel. However, this scheme requires twice the number of capacitors to store the image.
The voltage on each capacitor in the array is passed through a multiplexer (MUX) 8 to an Analog to Digital Converter (ADC) 9. The ADC 9 outputs digital values corresponding to the voltages on the storage capacitors, which represent the relative intensity of illumination upon the photo-sensors in the array. These digital values may then undergo Digital Signal Processing (DSP) 10 to, e.g., enhance the image contrast and reduce the number of storage elements needed to store the resultant image. A subsequent Correlator 11 compares the DCPed image data with prior image data, and navigation data reflecting the magnitude and direction of device motion is produced at 12.
In the example of FIG. 1, 2 separate storage capacitors are required to store the value for each photo-sensor in the array. Such storage capacitors are typically located on each side of the array, and require a relatively large amount of area on an Integrated Circuit (IC). This architecture is also susceptible to parasitic signal couplings, capacitor mismatch, capacitor leakages and charge injections, and can only store an image for a relatively short time without degradation of the image data. Moreover, this architecture presents problems with regard to digitally-oriented Application Specific Integrated Circuit (ASIC) technologies, which may involve high sub-threshold leakages and low power supply voltages. The ADC function is also performed in a serial fashion, i.e., one pixel at a time. The complete frame processing must occur quickly (within times on the order of 100 μseconds) and requires a high speed ADC for high speed applications (such as detection of computer mouse movements). Although it is possible to implement multiple ADCs and other digital circuitry components to parallel process multiple pixels, the multiple components required for parallel processing must have matched properties, which further increases cost. Such parallel processing also increases overall power consumption and die size.
Alternative photosensor array configurations for electronic imaging have been suggested. However, these alternative configurations are generally not well suited for motion detection applications in compact devices (such as, e.g., computer input devices), particularly when power consumption is a concern. In the context of digital photography (and other applications in which a relatively high resolution image is sought), processing speed is often less of a concern than image quality. In a digital camera, for example, a single “snap shot” may be taken at relatively infrequent intervals (i.e., separated by several seconds or more). Conversely, a motion detector must process hundreds of images (or more) every second. Moreover, many of these alternative photosensor array configurations draw significant power. Although high power consumption may be acceptable when there are relatively long intervals between images, and when multiple other processing functions are not required, high power consumption can be particularly disadvantageous in motion detection devices. In addition to processing many more images per second, motion detection devices must also process the image data to determine the occurrence of (and often the magnitude and direction of) motion, and must often power an independent light source. While excessive power consumption is generally undesirable, it is especially so when a battery supplies power. Electronic photography configurations also present problems in scaling an array to a smaller size. In order to obtain a highly detailed image, numerous circuit components are necessary, and such components require space.
As indicated, many of the problems with known alternative imaging designs result, at least in part, from attempts to increase image resolution. With photo-like image quality an unnecessary or less critical design parameter, lower power and more compact designs might be possible. To date, however, no known imaging system has attempted to balance the degree of pixel-level circuit components needed for accurate motion detection images with the simplicity necessary for rapid, low power operation in a compact size.